Semiconductor wafer bonding processes have been developed for bonding two silicon wafers together to form a new wafer, such as wafer 2 shown in FIG. 1A that includes a direct bond hybridization (DBH) structure 4. DBH processing may be used in the formation of a focal plane array comprised of a detector wafer 14 stacked on a read out integrated circuit (ROIC) 8, which includes analog and digital integrated circuits 6, resulting in a SiPIN hybrid sensor. Between the detector wafer 14 and the integrated circuits 6 may be found metal contact layers 10 and a metal interposer layer (e.g., interconnecting posts 16) with an insulating (e.g., oxide) layer 12 encapsulating the metal structures. Detector wafer 14 may be bonded to the ROIC 8 through oxide bonding that enables metal interconnecting posts 16 embedded within the insulating layer(s) 12 to form an interposer connection.
Additional information about an exemplary 3D stacked wafer may be found in “Third Generation FPA Development Status at Raytheon Vision Systems”, W. A. Radford, et al., Infrared Technology and Applications XXXI, Proc. of SPIE Vol. 5783, and/or data sheets related to the DBI® process developed by Ziptronix, Inc. (a subsidiary of Tessera Technologies, Inc.) and available at http://www.ziptronix.com/technologies/dbi/.
With reference to FIGS. 1B-1D, plating may be used to deposit product features, such as one or more interconnection metal post(s) 16, in a photoresist layer 13 prior to stripping the photoresist and depositing the insulating layer 12. Conventional plating bath manufacturers engineer their baths to achieve reasonably good plating height uniformity across a substrate, despite variation in product feature (e.g., trace lines, vias, etc.) sizes. There are, nevertheless, variations in product feature heights, such as the height hp of metal post 16′, which occur due to variations in the depositing processing conditions (e.g., variations in current distribution in electroplating.) The height hp of the respective posts 16′ and the insulating layers 12 of the detector wafer 14 and ROIC 8 need to be reduced within very tight tolerances to enable proper interconnection during wafer bonding in subsequent wafer stacking operations.
The DBH manufacturing process includes lithographic techniques that result in the formation of metal (e.g., nickel) post structures 16′ encapsulated in oxide insulating layers 12. To reveal the metal posts prior to bonding, each insulating layer 12 may be thinned from, for example, initial height hi (at time ti) down to desired height h2 (at time t2) using a wafer thinning process such as CMP.
CMP is often used to planarize and remove material from the insulating oxide layer 12 until the embedded post 16″ is revealed (such as shown in FIG. 1D.) With reference to FIG. 2, CMP typically utilizes abrasive slurry to planarize the surface of a wafer 20, through a combination of mechanical and chemical action. Generally, CMP involves pressing onto wafer 20 a polishing pad 22, which may be vacuum-mounted on a rotating carrier head 24. As the wafer 20 and polishing pad 22 come into contact, the surface of the wafer 20 is mechanically and chemically polished. A critical component of any CMP process is endpoint detection. Lacking in-situ direct feedback for measuring wafer thickness during CMP, conventional processes commonly estimate CMP rates and timing to complete a CMP process. However, variations in the chemical or mechanical composition of the slurry, the pad, or the wafer may cause the amount of time needed to polish to the desired depth to vary.
Due to optical interference from the underlying circuitry (i.e., multiple metal routing layers of oxide and metal), optical interferometry methods cannot be used in-situ to measure the actual height of the CMP thinned insulating layer 12. Accurate optical oxide height measurements on the ROIC typically cannot be made on the completed wafer. This may permit adjustment of operating parameters for future wafer processing runs, but it does not account for wafer to wafer variations. If CMP rate of material removal is greater than predicted for the wafer an excess of material will be removed, resulting in over-polishing of the layer and loss of product. Thus processing problems leading to unpredictable polishing rates leave no way to determine the thickness of the structure in-situ, resulting in potentially expensive (e.g., $50 k/wafer) yield losses.
The present implementations provide methods and structures directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.